To decrease the size and improve the performance of an electronic apparatus, the mounting density of a semiconductor chip or semiconductor device is being increased in recent years. The mounting density of a semiconductor chip is in many cases increased by mounting the semiconductor chip on a wiring board by wireless bonding, particularly, flip chip bonding. The mounting density of a semiconductor device is often increased by mounting the semiconductor device on a wiring board (which is different from a wiring board forming the semiconductor device. This wiring board will be referred to as “a mother board” hereinafter) by surface mounting. For semiconductor devices, various packaging methods suited to surface mounting such as a ball grid array semiconductor package have been developed. Flip chip bonding and surface mounting are advantageous in downsizing and micropatterning a semiconductor chip and semiconductor device, and increasing the number of pins. Flip chip bonding and surface mounting are also advantageous in increasing the operating speed of an integrated circuit or the like formed in a semiconductor chip or semiconductor device, since the wiring resistance can be made lower than that of wiring bonding.
To improve the performance and increase the operating speed of, e.g., a system large-scale integrated circuit (system LSI), it is possible to improve the performance and increase the operating speed by mounting a plurality of LSIs and passive parts on one semiconductor chip, rather than by improving the performance and increasing the operating speed by one LSI. For this reason, a system LSI (system on chip) of this type is beginning to be widely used.
When forming a semiconductor device by mounting a highly integrated semiconductor chip having a large number of pins on a desired wiring board, a large difference between the thermal expansion coefficients of the semiconductor chip and wiring board increases the internal stress of the semiconductor device by heat generated when an electric current is supplied to the semiconductor chip. This causes stress concentration in, e.g., the junction portion between the semiconductor chip and wiring board in the semiconductor device or the connecting portion between the semiconductor device and a mother board, so disconnection or the like readily occurs. As a consequence, the reliability of the semiconductor device or an electronic apparatus using the semiconductor device decreases. To obtain a highly reliable semiconductor device or electronic apparatus, therefore, a resin is often filled in the junction portion between a semiconductor chip and wiring board of the semiconductor device, in the junction portion between the semiconductor device and a mother board, and in peripheral portions of these junction portions, thereby reinforcing the junction portions.
Japanese Patent Laid-Open No. 64-32662 (reference 1) describes a semiconductor package structure (semiconductor device) which increases the reliability by interposing, between a semiconductor chip and wiring board (large board), a small board having a specific thermal expansion coefficient, i.e., a small board whose thermal expansion coefficient difference from the semiconductor chip is smaller than that from the wiring board (large board). The semiconductor chip is mounted on the small board, and a plurality of small boards each having the semiconductor chip are mounted on the wiring board (large board).
Although this is not an invention of a semiconductor device, Japanese Patent Laid-Open No. 8-167630 (reference 2) describes a chip connection structure in which an integrated circuit chip and wiring board are connected by direct through-hole connection by interposing an adhesive film between the integrated circuit chip and wiring board, and making the thermal expansion coefficient of the wiring board substantially equal to that of the integrated circuit.